New Tools Make PLL Analysis Easy!

Devices and systems are exceeding 1GHz operating frequency forcing tighter constraints on timing margins. To keep all of the critical elements in sync, system designers are relying heavily on precision PLL circuits to provide quality timing-reference.

By increasing our reliance on PLL devices, we must learn better ways to debug, characterize and test our synchronous systems. The Wavecrest SIA Family is uniquely qualified to debug, characterize and test PLL devices. The SIA Family combines high precision measurement and advanced analysis algorithms with high throughput to provide the most comprehensive PLL analysis solution on the market today.

The SIA Family can measure every critical characteristic of a PLL device including random and deterministic jitter, periodic jitter, adjacent cycle jitter, duty cycle, slew rate, voltage characteristics and PLL loop response.

When a histogram is non-Gaussian, the 1-sigma value is not an accurate representation of Random Jitter(RJ). Using the patented "Tail-Fit" algorithm Separate the components of Random Jitter(RJ) and Deterministic Jitter(DJ) from a histogram. (Figure 1)
View the long-term reliability of a signal and calculate the Total Jitter(TJ) at a specific BER or after a certain amount of time. (Figure 2)
Once the DJ component has been determined, use the Modulation analysis tool to quantify the Periodic Jitter(PJ). The FFT view shows the Spectral content of the jitter. This view shows only the frequency components of the jitter which allows quick, easy identification of jitter sources. (Figure 3)